My invention relates to packages for semiconductor chips, and more particularly to packages incorporating high thermal conductivity elements for drawing heat away from a power semiconductor chip.
Semiconductor chips that generate heat during operation in excess of about one watt are known in the art as "power" chips as distinct from "signal" chips, where power dissipation is usually much lower. Such heat arises primarily from I.sup.2 R conduction or switching losses in the chip. To avoid thermal damage, the heat must be removed from a power chip and transferred to, for example, a metallic heat spreader plate or heat sink. However, power chips must be electrically tested at rated current in order to determine significant characteristics, such as, in a bipolar transistor, the common emitter current gain, H.sub.FE, and the collector-to-emitter voltage at device saturation, V.sub.CE (SAT). These characteristics typically vary considerably from chip to chip, even though the chips are made in the same batch. Such electrical testing requires the chip to be operated at high levels of heat generation, requiring the chip to be mounted in a package incorporating high thermal conductivity elements for removing heat from the power chip.
A typical power chip package that is commercially available includes a high thermal conductivity dielectric substrate, such as alumina, with a single layer of solderable metal on its upper surface covering a large area of the substrate. The substrate is mounted on a metallic heat spreader plate to facilitate heat removal. That side of a power chip having only one large area electric terminal, for example, a collector terminal of a typical bipolar transistor, is positioned to face downward and is soldered to the solderable layer atop the dielectric substrate. One or more wires are then bonded to the one or more terminals on the reverse or upper side of the power chip and are connected to electrically isolated areas of the power chip that are suitable for interconnection to external circuitry.
The presence of the bonded wire(s) on the upper side of the chip undesirably precludes a high thermal conductivity element from being attached to such upper side. Additionally, the wires bonded to the upper side of the chip are too fragile to be directly connected to testing circuitry, and therefore such wires must be first attached to rugged lead structure which, in turn, can be directly connected to testing circuitry. For high current power chips, such rugged lead structure is so large that it cannot be supported solely by the dielectric substrate on which the power chip is mounted, but must have additional mechanical support from the metallic heat spreader plate onto which the dielectric substrate is also mounted. The individual leads of the rugged lead structure must be provided with appropriate electrical insulation, so that a complete (and costly) package must be assembled before chip testing is possible. The use of such power chip packages for chip testing in order to select a group of chips with similar characteristics is especially costly, since chips with undesired characteristics along with their packages are likely to be discarded.
An object of this invention is to provide a power chip package which is simple in construction and thus of reduced cost than presently-available power chip packages.
A further object of the invention is to provide a power chip package capable of removing significantly more heat from a power chip than presently-available power chip packages.
In accordance with a preferred embodiment of my invention, I provide a power chip package comprising a dielectric substrate, preferably of beryllia, and a plurality of sheet metal leads, preferably of copper, attached to a first side of the dielectric substrate, preferably by means of a eutectic bonding technique. The sheet metal leads are patterned in mirror image fashion to a plurality of terminals on one side of a power chip, for example, a power Darlington transistor. After the power chip is mounted on the sheet metal leads, as by soldering, heat generated in the power chip is drawn into the dielectric substrate via the sheet metal leads, and can be transferred to a heat sink by mounting the substrate thereon. The other side of the power chip, at least where it has one terminal, can be readily connected to external circuitry for testing simply by pressing a large area conductor against the exposed terminal.
In accordance with a more preferred embodiment of my invention, I include, in addition to the power chip package thus far described, a second dielectric substrate having a sheet metal lead attached thereto. This lead is adapted to be connected to a single, large area terminal of the power chip. This power chip package provides even more heat removal capacity than presently-available power chip packages, since the second dielectric substrate absorbs heat from the power chip.
In accordance with a still more preferred embodiment of my invention, I include, in addition to the foregoing power chip package, heat transfer means for transferring heat from the second dielectric substrate to the first one. The heat transfer means may comprise, for example, projections of one dielectric substrate which abut the other substrate when the package is assembled. This power chip package is capable of removing significantly more heat from a power chip than presently-available power chip packages, because heat removed from both sides of the power chip by the pair of substrates can be transferred to a heat sink.